Placement Oriented Program- "Foundation of VLSI Design"

• One of our unique program with 100% Success Rate in placement. Once you enroll for this program, exit is going to happen when you will have offerletter at your hand.
• 6Month of Course work + Placement activities/opportunities cycle
• Synopsys Tool Access - 24*7 Individual
• Available in Offline (Mysuru, Noida, Roorkee) and Online Mode
• FOR MORE INFO - VISIT OUT TRAINING SITE OR
• Fill the form to know more

Based on Skills

• Skill Development - Level 1
• Re-skilling | Upskilling - Level 1 & 2

Based on Level

• Level 1 - Fundamental
• Level 2 - Specilization & Advance
• Level 3 - Pro (100% Tool based)

Mode of Delivery

• Offline Classes
• Online - Live Classes
• e-Learning - Pre-recorded Courses

FOR MORE INFO - VISIT OUT TRAINING SITE

Workshop & Seminars & FDP (1-Week)

• The World of Logic Circuit with Circuit Verse
• Understanding of CMOS Practically
• RISC-V Processor

Training & Internship Program (3-Weeks to 8-Weeks)

• Physical Design using OpenSource Tool
• RISCV RTL to GDS
• ASIC Design and Verification

Long Term courses (12-Weeks)

• Physical Design using Synopsys Tool
• Foundation of VLSI Design

Customised Program

Based on company requirement, we can customise the different trainings. Please contact at support@vlsiexpert.com for more detail.

• VLSI Campus Interview Preparation
• Advance Topics - Like Static Timing Analysis

Short Term Training (1 week to 2 weeks)

• Physical Design
• Logic Synthesis
• Design Verification
• Static Timing Analysis

Long Term Training (3 Months to 4 Months)

• Physical Design & Static Timing Analysis
• Physical Verification
• Design Verification

Customized Training

Based on company requirement, we can customise the different trainings. Please contact at support@vlsiexpert.com for more detail.

Madhuparna Das

We can't predict our future. But we can make choices & wish that things placed in the right place. One of my students Madhuparna Das also dreamed similar thing long back and we (#VLSI Expert Family member) all feel proud that she is now in Cadence Design Systems. Like I always say- "Be Expert By Expert"

College: Accurate Institute of Management and Technology - Greater Noida
Year of Passing: 2018
Placement/year: Cadence /2018 (as Intern)
Current Status: In Cadence (Permanent)
Profile: STA Engineer

Geetika Singh

Understanding about #VLSI Industry & it's requirement before Training Vs after Training. One of my #student "Geetika Singh" placed in "Synopsys Inc" after successfully clearing 4-5 rounds. It's her #dream #company & I am happy that she cracked that. Her passion, efforts, hard-work & believe in herself are the only few reasons for her success.
#Fundamentals & #Basics are the foundation of every Industry but unfortunately, students are lacking big time in this area. As a VlsiExpert offline Training Program, I am focusing on this aspect. EDA tools can change, tool's command can change but tool's fundamental can't be changed. We are Engineers - "Tools should not command us - we should command Tools."
You should listen to this 2.5min Video & I can bet it will #motivate every fresher.

College: ABES Engineering College
Year of Passing: 2018
Placement/year: Synopsys /2018 (as Intern)
Current Status: In Synopsys (Permanent)
Profile: Standard Cell Layout Design

Suryansh Singh

Reskilling is something can be done at any point of time. Few people think twice before sharing with someone that they have to enhance their skills by joining some classes or courses. But in My opinion, you should feel proud.
VLSI Expert is one of the platforms for working professionals to enhance skills set. It can be a revision of basic concepts or maybe all together the development of a new skill-set. See the review of one of the #VLSI Expert family member (Surayansh) who have enhanced their Skillset and how it helped him.

College: ABES Engineering College
Year of Passing: 2018
Job in Synopsys: 2018 (as Intern)
Current Status: Permanent in Synopsys
Profile: Physical design kit validation Engineer

MORE TESTIMONIALS - PLEASE VISIT TRAINING WEBSITE

Rishu Shukla

https://www.linkedin.com/in/rishu-shukla-227631126/

College: ABES Engineer College
Year of Passing: 2018
Placement/year: Synopsys-Gatelength / 2019
Current Status: In Synopsys (Contractor)
Profile: Memory Layout Profile

When I look back on my journey of achieving what I want to be, I see the guidance, motivation and great support of my mentor Puneet Mittal sir which has led me finally to get into a VLSI industry. And a special thanks to Avnish Shukla sir for their help and support.When I was persuing b.tech I did not have an iota about VLSI and I never thought of getting into the core industry. Even when I get to know about VLSI then also I had doubts whether I will be able to achieve this or not. But one person who had a trust and belief on my capabilities was Puneet sir.
In VLSI EXPERT you don't just mug up the concepts and get a placement. You grow over here. Your personality, self belief, way of learning, attitude is developed over here. Just follow the instructions of Puneet sir and you will see a vast change in your learning and in all the other aspects.
In my case I had a doubt whether I will be able to achieve this or not one year back but he took out the best of me.He motivated me everytime whenever I felt low. Sir you are the reason I didn't give up. This journey is never be possible without you. Thank you for all your love and support.

Introduction to Static Timing Analysis & Timing Arc

• Importance of Timing Analysis, VLSI Flow Introduction & different stages where Timing analysis happen
• Different component of Timing analysis (Timing Budgeting,Timing Constraint,Timing Check,Timing Violations,Fixing of Timing Violations
• Introduction about different input and output files for STA
• Importance of Timing Arc & Timing Arc Representation in .LIB Files

Delay Introduction (Cell Delay and Net Delay)

• Introduction of Delay Concepts
• Combinational Path Delays,Sequential Path Delays
• Net Delay basic (Metal Wire Concepts,Metal Stack concepts)
• Gate Delay Concepts (Charging & Discharging concepts, Load related Concepts, Delay dependency on current of Inverter,Internal Capacitance,Input Capacitance and Output Capacitance concepts

Delay Models & Understanding Delays Libraries

• Gate Delay Models (How delay depends on Input Transition & Output Load,NLDM Library & CCS Library)
• Net Delay Models (Transmission Line Models,Elmore Model,Wire Load Model

STA Tool Delay Calculation Methodology

• Delay Calculation by STA tools (Path based Analysis and Graph Based Analysis)
• Pre-Layout Delay (using wire-load model) & Post layout Delay (using SPEF File) calculation
• Delay Calculation using Delay tables, Complexity across different corners.
• Dependency of Delay on different parameters (PVT Corners,Manufacturing defects,RC Corners)

Timing Paths, Timing Exceptions & Timing Constraints

• Various Timing Paths (Data Path, Clock Path, Asynchronous Path,Clock Group Introduction
• Representation of Timing path within Timing report
• Timing Exceptions (False path, Multicycle path)
• Clock Constraints,Input and Output Delay constraints

Setup and Hold Time

• Different Timing Terminology (launch/Capture path,Slew, Clock latency,Clock skew)
• Setup and Hold Time
• Setup and Hold Check and corresponding Equations
• Basic Timing Report

Advance Timing Concepts

• Gloabal Setup-hold time
• Onchip Variations (OCV),Advance onchip Variation (AOCV),Setup and Hold Check in case of OCV, AOCV
• CRP & CRPR
• Multi-Mode Multi-Corner timing analysis

Timing optimization & Timing Closure Methods

• Pre-placement (After synthesis) optimization
• Pre-CTS (during or after placement or floorplaning) optimization
• Fixing of Setup and Hold Violation at Logic Synthesis (front-end vlsi)

Post Layout STA (Backend) & Fixing Setup and Hold Violations Methods

• Post CTS or Pre-Route (After CTS)Optimization
• Signoff Timing or Post-Route (After Routing) Timing Closure

Module 1 : Digital Electronics

Digital basics (Revision of Engineering course work)

• Binary System, Logic Levels, Different Logic States, Noise Margins
• Combinational circuit & Sequential circuit,Frequency Divider/Multiplyer Circuit,Sequence Detector
• FSM (Meely and Moree Models)

Advance Digital (Implementation of Digital circuit in VLSI design)

• Designing of Different Logic gates/Combinational Circuit/Sequential elements using MUX
• PAL, PLA concepts, Tristate Buffers / Tristate Inverter,Clock Gating Concepts
• Standard Cell Library Concepts
• Logic Optimization

Module 2: Semiconductor Electronics

Semiconductor Overview

• Property & Parameter : (Doping/Impurities,Amount of Impurities, Different type of Region (N+/N++, P+/P++),Energy Bands, Fermi Level,Drift Current, Mobility)
• Semiconductor Devices : (Depletion region, Build In potential,Immobile Ions,Diffusion Current, Recombination)

Module 3: CMOS Design

CMOS Fundamental

• Basic : (Concepts of Vt in a MOS & Subthreshold Regions, MOS Electrical Parameters: Inout output characteristics,How Source/Drain Terminals are defined,Cross Section of NMOS,PMOS,CMOS,Finfet Vs Planner CMOS)
• Advance CMOS : ("Different factors on which Vt has dependency, Body Biasing, Channel Length Modulation", FInFet Concepts, W/L Ration Concepts (Parallel and Series Connection),Parameter Varaition (Fast and Slow Transistor) FF/SS CMOS, HVT / LVT / RVT Cells,Device Scalling)

CMOS Circuit Design

• CMOS Pass Transistor : (Switching Theory,NMOS and PMOS pass Transistor, Transmission Gate concepts, Pass transistor based problems)
• CMOS Circuit Design : (Designing of all Logic Gates, Combinational & Sequential Circuit)

CMOS Fabrication

• Cross Section of CMOS,Single Tub/ Twin Tub, Single Well
• Device Cap and Metal Cap / CMOS Fabrication Process (Step by Step)
• Shallow Trench Isolation (STI layer), Latch Up Concepts

Module 4: Linux

Linus Basic

• Development, Architecture and Features of Linux OS, Shell Support, Disk Usage and Login.
• Managing Disk Files & Directories,Managing Documents using Find command, filters,pipes & redirections
• Shell Programming,Shell within shell, Parameter handling & command substitutions. Functions – Recursion writing
• Shell Scripting: bash cshell,awk,sed
• VI editor concepts

Module 5: VLSI Automation and Scripting

TCL & Perl Scripting

• TCL & Perl Introduction and it's industrial use,Concepts of Wrapper,
• Procedure in TCL & regular expression
• File Handling, Read/Write Operation, Flow Control (Foreach, while, switches, for etc)
• Perl: List, Hash concepts

QOR and Reporting Concepts

• Reporting concepts & different analysis concepts
• Log file and different type of Messages in that ( ERROR Messages, INFO Messages, WARNING Messages)
• Regression Concepts,Version to Version Check , Accuracy Check, Golden Vs Test Result
• Automation For Validation
• How to create charts, read charts, Histrogram, Pi charts concepts

Module 6: C and C++

C language

• Introduction and Overview of C.
• Constant, Variables & Data Types,Operators & Expressions, Conditional, Multiway Branching & Looping, Arrays and Strings
• Input and Output Management.
• User Defined Functions, Structures and Unions.
• Pointers,Dynamic Memory Allocation and Linked Lists

C++ Programing

• Introduction & Overview of C++,Basics of Program writing.
• Arrays, Qualifiers, Reading Numbers and Bit Operations,Decision & Control Statements.
• C++ Preprocessor, Variable Scope & Functions, Advance Programming Concepts (File Input/Output, Debugging & Optimization, Operator Overloading, and Floating Point)
• Advance Data Types, OOPs (Simple & Advance Classes),Basic & Advance Pointers

Module 7: Logic Synthesis

Logic Synthesis (basic)

• Introduction to Synthesis, Basic Terminology
• Netlist Overview with libraries introduction (Target Library, Link Library)
• Concept of Synthesizable RTL, Mapping to Gatelevel Netlist
• Different way of Modelling combinational or sequential elements

Logic Synthesis (Advance)

• Timing constriant basic (Max Trans, Max Cap, Max Fanout, Min cap)
• Commonly Faced Issues during Synthesis
• CDC and LINT Concepts
• DFT insertion basics inside synthesis tool

Module 9: Verilog HDL

Digital Design Using Verilog

• VLSI Flow,Different Modeling Styles,Predefined Gate Primitives,Continuous Data Assignments.
• Hierarchy Creation, Module Instantiation and Mapping, Stimulus Creation.
• Multiway Branching & Generate Blocks.Delays, Event Control and Timing Regions at Higher Level of Abstraction.
• Compiler Directives,System Tasks & Functions
• Switch Level Modeling (Lowest Level Abstraction Level).
• User Defined Primitives (UDPs).Variable Change Dump (VCD),Specify Block.

Module 10: System Verilog

Introduction to System verilog

• Arrays, Structures and Data Types,Tasks and Functions New Features, Interfaces
• Program Control & Hierarchy, Hierarchy & Connectivity of modules.
• IPC (Inter Process Communication),Semaphore and Mailbox, Randomization,Programs & Clocking Block
• Functional Coverage,SVA (System Verilog Assertions),Verification Environment.
• Labs

Module 11: UVM (Universal Verification Methodology)

Introduction to UVM

• UVM Reporting,UVM Transaction, UVM Configuration,UVM Factory,UVM Sequences,UVM Transaction Level Modeling (TLM),UVM Callback.
• UVM Testbench (Testbench Top,UVM Test,UVM Environment,UVM Scoreboard,UVM Agent,UVM Monitor,UVM Driver,UVM Phases,UVM Sequencer

Module 12: Static Timing Analysis

Introduction to Static Timing Analysis & Timing Arc

• Importance of Timing Analysis, VLSI Flow Introduction & different stages where Timing analysis happen
• Different component of Timing analysis (Timing Budgeting,Timing Constraint,Timing Check,Timing Violations,Fixing of Timing Violations
• Introduction about different input and output files for STA
• Importance of Timing Arc & Timing Arc Representation in .LIB Files

Delay Introduction (Cell Delay and Net Delay)

• Introduction of Delay Concepts
• Combinational Path Delays,Sequential Path Delays
• Net Delay basic (Metal Wire Concepts,Metal Stack concepts)
• Gate Delay Concepts (Charging & Discharging concepts, Load related Concepts, Delay dependency on current of Inverter,Internal Capacitance,Input Capacitance and Output Capacitance concepts

Delay Models & Understanding Delays Libraries

• Gate Delay Models (How delay depends on Input Transition & Output Load,NLDM Library & CCS Library)
• Net Delay Models (Transmission Line Models,Elmore Model,Wire Load Model

STA Tool Delay Calculation Methodology

• Delay Calculation by STA tools (Path based Analysis and Graph Based Analysis)
• Pre-Layout Delay (using wire-load model) & Post layout Delay (using SPEF File) calculation
• Delay Calculation using Delay tables, Complexity across different corners.
• Dependency of Delay on different parameters (PVT Corners,Manufacturing defects,RC Corners)

Timing Paths, Timing Exceptions & Timing Constraints

• Various Timing Paths (Data Path, Clock Path, Asynchronous Path,Clock Group Introduction
• Representation of Timing path within Timing report
• Timing Exceptions (False path, Multicycle path)
• Clock Constraints,Input and Output Delay constraints

Setup and Hold Time

• Different Timing Terminology (launch/Capture path,Slew, Clock latency,Clock skew)
• Setup and Hold Time
• Setup and Hold Check and corresponding Equations
• Basic Timing Report

Advance Timing Concepts

• Gloabal Setup-hold time
• Onchip Variations (OCV),Advance onchip Variation (AOCV),Setup and Hold Check in case of OCV, AOCV
• CRP & CRPR
• Multi-Mode Multi-Corner timing analysis

Timing optimization & Timing Closure Methods

• Pre-placement (After synthesis) optimization
• Pre-CTS (during or after placement or floorplaning) optimization
• Fixing of Setup and Hold Violation at Logic Synthesis (front-end vlsi)

Post Layout STA (Backend) & Fixing Setup and Hold Violations Methods

• Post CTS or Pre-Route (After CTS)Optimization
• Signoff Timing or Post-Route (After Routing) Timing Closure

Module 13: DFT Concepts

Fundamental of DFT

• DFT ? Why, What, Who, When?
• Implementation of Digital Concepts in DFT & Different Terminology
• Test Concepts & Automatic Testing
• Timing Checks and Constraints, Timing concepts for DFT

DFT Basics

• Introduction to BIST (Built-In Self Test)
• Introduction to BIT (Built-In Test)
• Scan Chain Concepts, Boundry scan chain
• Introduction of ATPG (Automatic Test Pattern Generation)

Module 14: Low Power Methodology

Basic Concepts

• Power Domain Concepts, Different Device powers (Leakage power,Static Power,Transition power)
• "Power Related Cells(Retention cell,Level shifter,Isolation Cell and other special cells)
• Low power concepts - Why we need it, UPF / CPF concepts - Why we need it